The first is line structures at 20nm pitch with 13nm tip-to-tip critical dimension (CD) relevant for damascene metallisation, and the second is electrical test results of Ru lines at 20nm pitch obtained with a direct metal etch (DME) process.

These results, enabled in part by the EU’s NanoIC pilot line, not only mark a major milestone in advancing the single print capabilities of High NA EUV patterning, but they also underscore the pivotal role of the imec-ASML partnership in enabling the broader ecosystem that drives the High NA EUV transition to high volume manufacturing, unlocking the sub-2nm logic technology roadmap.

Imec had previously demonstrated 20nm pitch metallised line structures at the 2025 SPIE Advanced Lithography and Patterning back in February 2025 and has now been able to achieve 20nm pitch line structures with 13nm tip-to-tip (T2T) critical dimension (CD) with a single-exposure High NA EUV lithography step.

For the 13nm T2T structures, a local CD uniformity (LCDU) as low as 3nm was measured, marking an industry milestone.

The results were obtained with a metal oxide resist (MOR), which was co-optimised with underlayer, illumination pupil shape and mask selection.

According to Steven Scheer, Senior Vice President Compute System Scaling at imec, “Achieving these logic designs with single print High NA EUV lithography reduces processing steps compared to multi-patterning, lowering fabrication costs and environmental impact, and improving yield.

“These results support damascene metallisation, the industry standard for interconnect fabrication. T2T structures are an essential part of the interconnect layers, as they allow for interrupting the one-dimensional metal tracks.

“To meet the logic roadmap at 20nm metal pitch, the T2T distance is expected to scale to 13nm and below. while maintaining functional interconnects. Developments are ongoing to further scale T2T dimensions, with promising results for 11nm T2T, and to transfer the structures into an underlying hard mask – enabling true (dual-)damascene interconnects.”

To enable metallisation below 20nm, industry will likely move to alternative metallisation schemes.

As a second achievement, imec was able to demonstrate the compatibility of direct metal etch (DME) of ruthenium (Ru) with single exposure High NA EUV lithography. This achieved Ru lines at 20nm and 18nm pitch, including 15nm T2T structures and functional interconnects with low resistance. For the 20nm pitch metallised line structures, an electrical test yield of 100% was obtained.

“After the opening of the joint ASML-imec High NA EUV lab in Veldhoven, the Netherlands, imec and its ecosystem of partners have made great strides in advancing High NA EUV lithography and launching the industry into the angstrom era – backed by three years of ecosystem preparation,” said Scheer. “The presented results mark a new milestone, underscoring imec’s leadership in litho R&D. They also play a critical role in realising the European Chips Act’s ambitions for enabling sub-2nm logic technology nodes.

“In close collaboration with the imec-ASML High NA EUV ecosystem, which includes leading chip manufacturers, equipment, material and resist suppliers, mask companies, and metrology experts, we continue to jointly optimise High NA EUV lithography and patterning in support of the logic and memory roadmaps.”

By: DocMemory
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