The NanoIC pilot line, a European initiative coordinated by imec for accelerating innovation in process technologies beyond 2nm, has released the N2 P-PDK v1.0, an important update of its N2 Pathfinding Process Design Kit (P-PDK).

This new version introduces several new features, including a library of 29 SRAM memory macros, allowing designers to explore and benchmark system-on-chip (SoC) designs with frontside and backside power routing.

By adding the SRAM macros in the design options, the N2 P-PDK v1.0 marks an important milestone in enabling research, learning, and design exploration on advanced and future nodes.

NanoIC adds SRAM to 2nm PDK

IAs chip technologies scale beyond 2nm, the ability to explore full architectures with novel technology enablers becomes increasingly important.<

SoCs, integrating logic, memory, and interconnect capabilities into a single chip, are the backbone of a wide variety of digital applications, from smartphones and AI accelerators to automotive controllers.

However, early-stage SoC design exploration is often constrained by limited access to complete and realistic design kits that include advanced or future technology scaling boosters such as power delivery networks.

This gap makes it difficult for designers to validate architectural concepts, experiment with emerging technologies, or to train the next generation of chip designers on advanced nodes.

NanoIC’s low-barrier N2 P-PDK v1.0 aims to bridge this gap, offering instant access to a wide variety of new design features, including a portfolio of 29 ready-to-use SRAM macros with both frontside and backside power routing configurations.

This dual configuration enables designers to experiment with and optimize memory integration within realistic, advanced power networks. As a result, NanoIC’s N2 P-PDK v1.0 now provides the building blocks of a complete SoC as well as the architectural context to explore how those blocks interact within realistic power networks.

It enables users to move beyond simple logic design and explore and validate full SoC systemsthat reflect the challenges and opportunities of next-generation semiconductor design.

By making these advanced features freely available to academic researchers, startups, and design teams, NanoIC significantly lowers the barriers to innovation, empowering the development of next-generation applications, and strengthening Europe’s position in the global semiconductor landscape.

“This v1.0 version of our N2 P-PDK enables designers to evaluate the impact of new technology features and integration options on their designs before they exist in foundry offerings. It provides a unique environment to connect technology pathfinding with practical design enablement, ensuring that breakthroughs in device research translate into system-level advances,” said Marie Garcia Bardon, department director at imec and work package leader within the NanoIC pilot line, summarizes.

Building on the learnings from the previous N2 P-PDK, this release lays the groundwork for future PDK iterations, launching additional advanced logic, memory, and interconnect PDKs in the coming years.

The roadmap includes future versions of the N2 P-PDK, as well as upcoming A14 and A7 logic P-PDKs, eDRAM and SOT memory PDKs, and advanced interconnect solutions (RDL, hybrid bonding, interposers), empowering innovation across the full spectrum of next-generation chip technologies.

To support designers in exploring the full capabilities of the N2 P-PDK v1.0, a dedicated workshop will be organized on March 25-26, 2026. This session will offer a theoretical framework, followed by hands-on training sessions, using two different EDA tools: Cadence and Synopsys.

Participants will gain insights into the SRAM memory macros, updated design rules, and system-level integration strategies.

By: DocMemory
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