Imec has demonstrated what it describes as the first functional three-dimensional implementation of a charge-coupled device (CCD) for memory applications, marking a potential step forward in addressing growing data demands driven by artificial intelligence.

The research, presented at the 2026 IEEE International Memory Workshop, centres on a 3D CCD device built using an indium gallium zinc oxide (IGZO) channel. The structure features vertical memory holes formed through a stack of three word lines, which act as phase gates. According to imec, the device successfully achieved charge transfer speeds exceeding 4MHz, confirming its operational viability.

The development comes as demand for memory continues to rise sharply, particularly in AI systems where large volumes of data must be processed and transferred efficiently. Conventional DRAM technologies are increasingly constrained in their ability to maintain cost efficiency at scale, prompting research into alternative architectures.

Imec’s approach leverages manufacturing techniques derived from 3D NAND flash, enabling high-density memory structures while maintaining relatively low production costs. This architecture could support the development of so-called CXL type-3 buffer memory, which is designed to provide shared memory resources across multiple processors through high-bandwidth interconnects.

Maarten Rosmeulen, programme director for storage memory at imec, said the technology offers a route to higher density and scalability. “The potential of this CCD device to be used as a buffer memory lies in its ability to be integrated in a 3D NAND Flash string architecture – the most cost-effective way to achieve a scalable, high bit density estimated to go far beyond the DRAM limit,” he said.

The device uses vertically aligned memory strings formed via a “punch-and-plug” fabrication process, with data represented as charges transferred along the IGZO channel. These charges can be moved between gates using a pulsed voltage scheme, enabling serial data storage and transfer.

Rosmeulen added that the device’s characteristics could align well with AI workloads. “Unlike byte-addressable DRAM, our 3D CCD device is designed to provide block-level data access, which is better suited to modern AI workloads,” he said. He also noted that the technology offers advantages including low power operation, long data retention and high endurance.

Imec previously demonstrated a two-dimensional proof of concept in 2024, but the latest results represent the first successful 3D implementation. The organisation is now working to expand the number of word lines and improve readout performance.

The project is expected to move into further development with industry partners, as researchers look to assess its potential as a next-generation memory solution for AI systems.

By: DocMemory
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