Cadence Design Systems Inc. and Samsung Foundry expanded their multi-year collaboration focused on second-generation 2nm process technology and 3D-IC design enablement for AI infrastructure, high-performance computing, and intelligent edge devices.

The companies said they have developed a broader portfolio of memory and interface IP and expanded certification of Cadence’s digital, custom, 3D-IC, and system design and analysis flows for Samsung Foundry’s second-generation 2nm node. The platform is intended to provide signoff-ready design capabilities for next-generation AI systems spanning data centers, edge computing, robotics, and other physical AI applications.

The collaboration extends earlier work announced in 2025 around certified Cadence tools and IP on Samsung Foundry nodes. The new agreement adds support for NVIDIA NVLink-C2C-enabled interconnect technology and CUDA-X GPU-accelerated libraries across high-speed SerDes, PCIe, UCIe, and leading memory interfaces on the second-generation 2nm process.

AI infrastructure and physical AI are pushing the industry into advanced node and 3D-IC designs that demand far more capacity, integration and signoff confidence than ever before.

“With this next phase of our Samsung Foundry collaboration, we’re giving joint customers a production-proven platform to deliver the next-generation of AI and HPC systems to market faster,” said Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence.

Samsung Foundry said demand for advanced AI designs is driving adoption of its second-generation 2nm technology.

“Customers are increasingly drawn to Samsung Foundry’s second-generation 2nm for leading-edge AI designs that must keep pace with the exploding demand across AI infrastructure and emerging physical AI applications,” said Jongshin Shin, executive vice president and head of Foundry Design Platform Development at Samsung Electronics. “Our expanded Cadence partnership delivers a robust semiconductor and 3D-IC platform with advanced Memory, Interface IP and AI-optimized flows for superior performance, efficiency and innovation.”

The certified flow on second-generation 2nm includes Cadence Innovus for digital implementation, Virtuoso Studio for analog and custom design, Integrity 3D-IC Platform for system planning and implementation, Voltus IC Power Integrity Solution for power analysis, and Quantus Extraction and Tempus Timing for signoff.

Cadence said the flow supports advanced 2nm design features including glitch power optimization and smart hierarchical implementation to improve performance, power, area, and turnaround time.

For Samsung’s 3D Cube-H technology, the companies are enabling a full planning, implementation, and signoff flow for hybrid copper bonding. The flow includes Cerebrus Intelligent Chip Explorer, Integrity 3D-IC, Innovus, Voltus, and Pegasus Verification System, along with silicon interposer auto-routing and optimization.

NVIDIA is using the expanded Cadence-Samsung platform for high-bandwidth interconnect and accelerated computing designs.

“As AI workloads scale and system architectures grow more demanding, the semiconductor ecosystem depends on tools and platforms that can keep pace with simulation and design complexity at advanced nodes,” said Timothy Costa, vice president and general manager of computational engineering at NVIDIA. “By leveraging Cadence’s GPU-accelerated design flows on Samsung Foundry’s second-generation 2nm platform, we’re optimizing the performance and delivery of next-generation AI architectures and high-bandwidth interconnects.”

Ambarella is also developing a next-generation 2nm edge AI platform using the companies’ PCIe 5.0 IP and design flows for robotics, drones, autonomous systems, and advanced sensing applications.

“Our collaboration with Cadence and Samsung Foundry to deliver IP for PCIe 5.0 for our next-generation 2nm edge AI platform has been critical as we address the design, verification and manufacturing complexity of this node,” said Chan Lee, chief operating officer at Ambarella. “Having a signoff-ready, co-optimized IP and tools solution, together with a robust, production-proven design kit and PDK, enables our teams to move forward with confidence, reduce risk and stay focused on accelerating innovation in low-power AI perception, physical AI and intelligent edge computing.”

By: DocMemory
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