Tuesday, January 14, 2003
Toshiba America Electronic Components is rolling out a new generation of pseudo SRAMs that is target for designers of mobile devices, especially 2.5G/3G cell phone makers looking to minimize power consumption.
The 128-Mbit devices are a follow on to Toshiba's line of 32-Mbit and 64-Mbit chips released in late 2001. These offerings fit into a developing trend for multi-chip packages that combine NOR flash, NAND flash and PSRAM, which will be key to future products in the mobile and consumer electronics markets.
Toshiba seems to have landed an early punch with its 128-Mbit chips; devices based on an 8-word page access mode that include partial array refresh to reduce standby power consumption, which weighs in at a maximum of 250 microamperes, and can go as low as 3-microamps in deep power down mode.
“Toshiba offers the highest density PSRAMs available which makes them the perfect answer for memory-intensive, feature-rich mobile systems,” said Paul Liu, senior manager of communication memory products at TAEC. “The new design boosts performance while reducing power consumption and is rapidly making these features the most popular solution for next-generation wireless applications,” he added.
Toshiba is due to start sampling the devices this month, and plans the ramp to volume production for March using a 0.17-micron process. The first device, labeled TC51WHM716AXBN, uses a single power supply with a voltage range of 2.6-V to 3.3-V for both core and input/output (I/O). It has a 70-nanosecond access time. The second device, the TC51WKM716AXBN, supports the same core range, a 1.8-V I/O, and a 75-ns access time.
Both devices are 8-Mbit x 16 and come packaged in a 9 x 12-mm, 69-ball fine pitch ball grid array and can be incorporated into stacked multi-chip packages that include SRAM, NOR and NAND flash.
By: DocMemory
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