Thursday, January 16, 2003
Intel has changed the release schedule for its Itanium chips and moving the launch date of the Itanium with two separate processors to 2005 from 2007.
Itanium 2 ranks with the best server chips in the market, but the new release schedule will enhance the chip's attractiveness and put pressure on competitors to step up their own schedules, something that historically they have been loath to do.
Intel's "design teams and design resources are well stocked, so they can do a shrink early or do a dual-core (chip) early. They have a lot of leeway that would stress out a Sparc development team," Eunice said, referring to shrinking the size of components on a chip and to Sun Microsystems' UltraSparc processor.
Under the new schedule, Intel will release this summer, Madison, a souped-up version of the current Itanium 2 with 6MB of level three cache, according to Jason Waxman, marketing manager for enterprise processors at Intel. Increasing the cache, a reservoir of memory located on the processor, generally enhances performance.
The chip, which will contain around 500 million transistors, will run at 1.5GHz. Madison, like the entire Itanium family, is a 64-bit chip, meaning that it can digest data in 64-bit chunks. 64-bit chips typically fit into the most expensive and powerful servers.
Soon after, Intel will release Deerfield, an energy-efficient Itanium 2 for rack and blade servers.
Then, in 2004, the company will come out with a new version of Madison that will contain 9MB of level three cache. Now most server chips come with 1MB of cache.
By: DocMemory
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