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Altera marching onto 0.9 micron FPGA
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Monday, January 20, 2003
Altera Corp. is developing a new field-programmable gate array (FPGA) architecture geared for the 90-nanometer process technology, which is expected to tape out in late 2003, company officials said.
The architecture would be Altera's third in two years. Last year, Altera unveiled two product lines under the Stratix and Cyclone brand names, both of which are being produced using Taiwan Semiconductor Manufacturing Co.'s (TSMC) 0.13-micron process technology.
Altera officials said 90-nm process technology is so different from 0.13 micron that it makes more sense to create another architecture from scratch than to migrate existing products to the new design rules. One reason is that the cost of creating derivative mask sets for the 90-nm node is getting too high. Another is that the voltage for products in the respective processes changes from 1.5 to 1.2 volts, which means a significant redesign.
"If you change the Vcc, you basically have to redesign your chip," said Tim Colleran, Altera's vice president of marketing. "It's just as painful as coming out with a new architecture."
Another big change will be the addition of low-k dielectric materials to the copper metallization process as a way to reduce wires capacitance. Chips based on the new architecture will incorporate the Black Diamond low-k material, which has a k-value of 2.9. Today, Altera uses FSG, which has a k-value of 3.7.
TSMC is expected to make low-k standard on its 90-nm process technology as Altera and other chip companies start to worry about the ill effects of higher off current. If no steps are taken to cap state leakage at 90 nm, it could get five times worse than leakage at the 0.13-micron node, said Francois Gregoire, Altera's vice president of technology.
At the transistor level, Altera will take measures to mitigate the ill effects of off-state leakage, including tuning transistors for higher operating voltage, making use of different gate-oxide thicknesses and adding more threshold-voltage variations, Gregoire said. At the architectural level, Altera is trying to use high-leakage transistors sparingly, assigning them to the "critical paths" that need the most performance, Colleran said.
But expect some performance degradation when battling I-off current. "You get to the point where you have to trade off performance for power," Gregoire said.
Surrounding the metal with low-k dielectric material can help reclaim some of that lost performance. Altera said it will optimize metal of its 90-nm chips to work with the low-k materials, which should boost device performance by 10 percent.
By: DocMemory
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