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Intel to merge GPS, Wi-Fi and other functions into single processor chip
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Monday, February 10, 2003
At the Intel Developer Forum (IDF) later this month, Intel Corp. is expected to provide a sneak preview of its new Internet-on-a-chip product line, 32- and 64-bit processors, and a hybrid "location awareness" technology.
The company is expected to expand its radio-frequency (RF) thrust, by talking about a research effort that combines global positioning system (GPS) and "location awareness" technologies. The disclosure will be made at IDF, which takes place from Feb. 18-21 in San Jose. The theme of this year's IDF is "Accelerating Convergence: Innovations in Communications and Computing."
In the location-awareness front, Intel's concept is to combine GPS and triangulation based on a plethora of 802.11 "hot spots," said Pat Gelsinger, senior vice president and chief technology officer corporate technology group at Intel.
Intel's R&D effort is a "fusion of the two technologies," Gelsinger said. "This is all lab stuff right now," he said in an interview with SBN today.
Also in the interview, Gelsinger and other Intel executives provided a sneak preview of the company's program at IDF. For example, during the keynote address at IDF on Feb. 18, Intel CEO Craig Barrett is expected to address Intel's previously stated efforts to "focus on staying one generation ahead of competition in technology, manufacturing and product development," according to the Santa Clara-based company.
On the product front, Intel is expected to disclose more details about its long-awaited, Internet-on-a-chip--codenamed Manitoba, which combines a baseband processor, flash memory, and other components on the same device.
Manitoba is a device that has "a high level of integration," said Gadi Singer, vice president of the Wireless Communications and Computing Group General Manager of the PCA Components Group at Intel.
Singer declined to elaborate on Manitoba, but confirmed the chip is based on XScale, its embedded RISC processor.
The company will also preview its code-named Deerfield chip, a low-power, 64-bit version of its Itanium2 processor family. Deerfield is a low-power version of its code-named Madison processor, which is a 64-bit chip that will formally ship in mid-2003.
And not to be outdone, it will talk about Prescott and Dothan, which are 32-bit processors based on 90-nm technology for the desktop and notebook computer markets, respectively. It will also disclose more details about the chip sets for Prescott, dubbed Springdale. Dothan is a follow-on to Banias, its next-generation mobile processor, based on 130-nm technology. Banias is expected to ship in March.
By: DocMemory
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