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Intel goes for dual-core processor
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Tuesday, February 11, 2003
Intel Corp. here disclosed more details about its new, revamped roadmap in the 64-bit processor arena, including some key specifications for its long-awaited Madison and Montecito chips for high-end servers and "mainframe-class" systems.
The microprocessor giant also disclosed the development of a new "arbiter" bus technology designed to manage two or more processor cores in the same IC package.
Both Madison and Montecito from Intel are expected to compete against 64-bit processors from Advanced Micro Devices, IBM, and Sun. AMD will roll out its first 64-bit processor for high-end servers in April, but it has delayed the introduction of its 64-bit processor for desktops by several months.
During a press event last week in San Francisco, Intel was quick to point out that it is on track to ship its latest 64-bit processor by mid-2003. Code-named Madison, the chip is part of the company's Itanium2 family of 64-bit processors.
For the first time, the company disclosed it would offer three chips in the Madison lineup--each with different clocks speeds and cache sizes. Intel will disclose more details about Madison at this week's International Solid-State Circuits Conference (ISSCC) in San Francisco.
The company also elaborated on its previously announced plans to revamp its Montecito 64-bit processor line. As reported last month, Intel was originally supposed to roll out the Montecito processor in 2004, but it will now delay the 64-bit product until 2005.
Montecito was supposed to be a single-core device, based on 90-nm process technology. Now, Intel plans to roll out a new version of Montecito, based on a dual-core architecture, in 2005.
Originally, Intel entered the 64-bit processor arena by rolling out its code-named Merced device a couple of years ago. Co-developed by Intel and Hewlett-Packard Co., the chip was late to the market and experienced little success, according to analysts.
In mid-2002, Intel rolled out the follow-on to Merced, code-named McKinley--which is a 1-GHz, 0.18-micron device. Intel refers to the McKinley chip as the Intanium2.
The follow-on to McKinley is called Madison, which is due out in the summer of 2003. The 410,000-million-transistor chip is a single-core, 1.5-GHz device, based on 0.13-micron technology.
At the press event last week, Intel disclosed that it would offer "three skews" in the Madison family. There will be three separate Madison chips, with L3 cache sizes of 3-, 4-, and 6-MB, said Nimish Modi, general manager of the Enterprise Processor Division for Intel, based in Santa Clara.
Modi declined to comment on the clock frequencies for the upcoming chips. "We will have three different products with Madison," Modi said. "The goal is to offer OEMs a wider choice."
The next 64-bit chips on Intel's roadmap are Madison 9M and Deerfield, which are believed to be due out in 2004. Madison 9M is a 64-bit processor with 9-MB of L3 cache, while Deerfield is a lower-power version of Madison for rack-mounted systems. "We feel they will have a percentage bump over Madison," Modi said.
Then, in 2005, Intel will unveil the dual-core Montecito. Each core will have a processor and L3 cache in the same package. Intel has also developed what is calls an "arbiter" bus technology, which will manage two cores as one systems bus.
The "arbiter" itself appears to be an internal bus that will interface to the overall systems bus. The "arbiter" technology will enable a processor to support twice the cache over previous devices, Modi said.
Little else was disclosed about the "arbiter" but the technology is key for high-end servers. "The fundamental driver is the cache," he said. "You get significantly better latencies with more on-die cache."
The "arbiter" will support the dual-core Montecito, but Intel dropped hints that it may be required to handle multi-core processors. "We are not ruling out multi-core systems in the future," he said.
In fact, Intel already presented a paper about a four-coreItamium2 processor in a keynote address at last year's Microprocessor Forum.
By: DocMemory
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