Friday, February 14, 2003
Engineers at IBM are preparing another attack on SRAM territory with an improved embedded DRAM (eDRAM) technology intended to make ASIC and high-performance processor designers take another look at the sometimes controversial technology.
IBM introduced a 144-Mbit DRAM on Wednesday (Feb. 12) with a cycle time of 5.6 nanoseconds, a data rate of 1.4 Gbits/second per pin and a die size of 121 mm2. The company asserted that its new architecture enables the DRAM's I/O bandwidth to compete with high-performance SRAMs, yet with an eightfold density improvement over its SRAM predecessors at IBM. Consequently, IBM's memory evangelists are predicting an increase in the instances where embedded DRAM replaces conventional SRAM, especially in high-performance processors such as Intel Corp.'s Itanium line.
"In some of IBM's servers, such as the X Series, the L3 cache is all embedded DRAM," said Subramanian Iyer, manager of IBM's System Scale Integration and a leader of its embedded DRAM initiatives. "I would predict that in the future, the L3 cache for any high-performance processor is going to be an embedded DRAM. You just cannot afford anything else."
In a paper presented Wednesday at the International Solid-State Circuits Conference, IBM SRAM design engineer Harold Pilo described a new scheme for speeding up eDRAM access time that IBM will apply to all future implementations. The architecture uses an early write technique to reduce the overhead needed for writing to the memory cell. Usually, the process of reading the cell, writing to sense amps, and then starting a refresh to the cell represents 15 percent of the word line active time, Pilo said. "We took that away. We are still write-limited, but by a very slight 2 percent," he said. "This is the fastest standalone DRAM in the industry, by far."
By: DocMemory
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