Friday, March 28, 2003
Chinese organizations are rushing to collaborate with electronic design automation (EDA) vendors of the United States.
Semiconductor Manufacturing International Corp (SMIC), a Chinese IC foundry, has made agreements with two major EDA vendors, Cadence Design Systems, Inc and Synopsys, Inc this month. Both agreements are related to the whole design flow from RTL to GDS II.
Also, SMIC made an agreement with Mentor Graphics Corp, the third major EDA vendor. SMIC choose Mentor's tools, including the Calibre IC mask layout verifier, IC Station integrated IC deign system, and Eldo circuit simulator.
These tools were standardized for internal production of SMIC. Also, SMIC announced this time that it adopted Hercules IC mask layout verifier from Synopsys. SMIC uses Hercules as one of the tools for layout verification and sign off.
Synopsys unveiled another collaboration. The company and the Chinese Academy of Sciences (CAS) announced they have signed an agreement to build an advanced system-on-chip (SoC) laboratory in Beijing. They claim the lab will be the first facility of its kind offered by CAS and an EDA provider in China.
The lab will use Synopsys' design implementation and verification tools to provide CAS with design and education resources to develop ICs at 0.13-micron. Training and use of the SoC lab will be offered to researchers and graduate students at more than 10 institutes supported by CAS. After the technical lab is established, Synopsys and CAS plan to discuss future cooperation on joint development with respect to 0.09-micron IC design technology and flow.
Synopsys is highly active in China. As for Cadence, it has made some announcements for training in China last spring.
By: DocMemory
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