Intel Corp. here today (April 10, 2003) announced a new chip-scale packaging (CSP) technology that enables OEMs to stack up to five die with package heights as low as 1.0-mm.

At the same time, Intel has rolled out 13 "standard packaging products" based on its new five-die, chip-stacking technology, dubbed Ultra-Thin Stacked Chip-Scale Packaging (CSP).

"In the past, stacking has been a customized business," said Scott Dunagan, marketing manager for Intel's Flash Products Group. "As more and more customers use stacked packages, we are moving chip-stacking technology towards a standard products business," Dunagan said in an interview.

Intel's packaging technology enables handset makers and related OEMs to develop small form-factor products with greater memory capacity and lower power consumption.

Claiming to be half the size of its previous four-die chip-stacking technology, Intel is gearing its new Ultra-Thin CSP offering for a range of products. Applications include small, feature-rich handsets that include color liquid-crystal displays and cameras.

Intel's stacked-CSP products enable OEMs to stack a combination of chips, including its multi-level cell (MLC) flash-memory technology, dubbed StrataFlash. The packaging technology is especially geared for the 1.8-volt version of StrataFlash. Intel is shipping 256-megabit StrataFlash parts, with 512-Mbit densities due out later this year and 1-gigabit chips in 2004.

The packaging technology also enables OEMs to stack SRAM, PSRAM and LP-SDRAM. "It allows us to stack five die in a 1-mm high package this year and a 0.8-mm package next year," Dunagan said.

In comparison, Intel's previous CSP offering was a four-die stacking technology that enabled package heights of 1.6-mm and a thickness of 7 mils. "With Ultra-Thin CSP, we are shaving that down to 3 mils," he said.

To enable this thickness, Intel has deployed a tape substrate and a wafer thinning technique. The company builds these packages by "grinding down" the back side of a silicon wafer with a mechanical grinding wheel until about 90 percent of the silicon is removed, according to Intel.

Meanwhile, Intel is rolling out 13 "standard packaging products," based on this technology. Intel Ultra-Thin Stacked-CSP products featuring its 1.8-Volt StrataFlash are currently sampling, with production volumes starting in third quarter of 2003. Pricing will vary by specific flash and RAM memory combinations.

By: DocMemory
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