Both Infineon Technologies and Micron Technology released specifications for RLDRAM II, a reduced latency memory optimized for networking applications.

The two companies are offering devices in standard 144-ball flip chip ball grid array packages. At 400-MHz, the eight-bank architecture achieves a peak bandwidth of 28.8 Gbps using a 36-bit interface with 20 nanoseconds in access latency. The specification includes common or separate I/O, and programmable output impedance.

A marketing executive at Micron said the new specification meets the needs of Ethernet and networking system designs with data rates of 10-40 Gbps.

By: DocMemory
Copyright © 2023 CST, Inc. All Rights Reserved