However, questions remain whether the MRAM cell size can be scaled quickly enough to be competitive.

A.R. Sitaram, a director of the MRAM alliance based at Hopewell Junction, N.Y., presented test MRAM arrays using 0.18-micron technology. He said it was the first public disclosure of MRAMs made on 0.18-micron design rules on a standard logic process.

A 128-Kbit prototype array has a cell size of 1.4 square microns, with an access time of 5 nanoseconds and a write pulse of 5 ns. Endurance is at least two orders of magnitude better than flash technology, he said. The power required to write a cell is 6 milliAmperes, which Sitaram conceded “is still somewhat high.” He said the alliance team is working on ways to improve the thickness of the switching layer to reduce power consumption.

Asked during the question-and-answer period following his presentation how the cell size could be scaled, Sitaram was deliberately vague, saying that the IBM-Infineon team has several novel ideas that it is working on.

The scaling challenge is great, said Shinichiro Kimura, a Hitachi manager who discussed non-volatile memory technology at a short course on the subject Monday. The best-reported MRAM cell size to date is 0.6-square micron, and Kimura said MRAM manufacturers need to shrink the cell size to about 0.1 square micron to be successful.

By comparison, cutting edge six-transistor SRAM cells are about one micron square at 90-nm design rules, and DRAM cell sizes are in the 0.2 sq. micron range at 90-nm. At the VLSI symposium, a DRAM cell size of 0.11 sq. micron was discussed by Toshiba engineers using 65-nm technology.

IBM and Infineon formed their MRAM alliance in late 2000. A fairly small team of about 20 people is working at various sites in New York, Almaden, Calif., and Munich. The partners have been working without fanfare for the past two years, publishing little, so the papers at the VLSI meeting here are a form of public reaffirmation of the IBM-Infineon commitment to the non-volatile MRAM technology. Some analysts had feared that the companies had pulled back their investments in MRAM development, but those doubts were put to rest here.

The two parent companies announced recently that they would concentrate MRAM manufacturing activity at a joint venture company they operate in Corbeil-Essonnes, France, called Altis Semiconductor SA. That facility provides the development team with a modern logic fab which uses copper interconnects for MRAM product development.

Sitaram, an Infineon staff member, surprised many at the VLSI meeting here by saying that the IBM-Infineon team used reactive ion etch (RIE) for definition of the magneto-tunnel junction, rather than ion milling, which has been used for some technology demonstrations.

The partners used modified commercial sputtering equipment for deposition of the ultra-thin magnetic and insulation layers. The platinum manganese magnetic layers, at about 1.2 nm (12 Angstoms) thick, and the aluminum oxide insulation layer, must be extremely uniform across the entire 200-mm wafer surface.

One challenge with MRAMs is to switch one MTJ without “flipping” the polarity of an adjancent bit. Bill Gallagher, senior manager of the magneto electronics team at IBM Research, said the IBM-Infineon team has been able to control the switching boundary within a 2 percent range across the array.

IBM, in cooperation with Infineon, has two parallel projects ongoing in magneto RAM (MRAM) development.

The work presented at the VLSI symposium is aimed at embedded memory applications, matching one transistor with one magnetic tunnel junction (MTJ). The 1T/1MTJ approach is optimized for switching speed in embedded applications.

The second approach is a zero transistor effort aimed at mass storage applications, replacing flash with MRAM, Gallagher said. That approach uses the word lines and bit lines to control access to a single cell. The zero transistor approach, also known as a crosspoint architecture, could stack multiple MTJs, doubling the density of the 1T/1MTJ approach.

“It is a stackable approach. We could have two to four MTJs, or six to eight, stacked vertically, depending on how we approach it. But that is further out. There is some synergy between the two efforts, but the crosspoint is a second generation technology and it is not the easiest to implement,” Gallagher said.

Motorola Inc., considered the leader in MRAM development, has been developing a 4-Mbit MRAM array. Motorola also is sharing its MRAM technology with STMicroelectronics and Philips Semiconductor at their joint process development center in Crolles, France. Besides IBM-Infineon, other companies working on MRAM technology include Cypress Semiconductor, NEC, Samsung Electronics, Sony Corp., and Toshiba.

By: DocMemory
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