Toshiba Corp. today announced that it has developed and verified the operability of a memory cell technology for embedded DRAM system LSIs on SOI wafers.

With plans to apply the new technology to mass production of system LSIs for broadband network applications in 2006, the company said that it has experimentally fabricated a 96Kbit cell array and verified the operability with "sufficient characteristics" required for embedded DRAM system LSIs on SOI.

While full details were presented at the VLSI Symposium in Kyoto, Japan, on Thursday, Toshiba today said it succeeded in forming embedded DRAM system LSI on an SOI wafer by developing a new DRAM memory cell technology that makes use of the characteristics of SOI wafer itself, eliminating the necessity of capacitors where current DRAM cell stores data. The new memory cell technology, dubbed floating body cell (FBC), will be used for embedded DRAM system LSI for the 45nm generation on, the company said.

Since the transistor works as both capacitor and electric switch, the cell area is half that of a conventional DRAM cell, the company claimed. Toshiba further said that the new process is compatible without any degradation in the performance of systems LSI, because a buffer layer of polysilicon is formed in contact area in memory cell.

The experimental 96Kbit cell array achieved successful operation in all bits, a 36-nanosecond access time, 30-nanosecond data switching time and 500-millisecond data retention time at 85 degrees C, Toshiba said, adding that such results prove FBC technology can be applied to system LSI integrating DRAM cells with megabit or greater memory capacity.

By: DocMemory
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