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Micron Technology announced that it will sample a 288-Mbit reduced latency DRAM II operating in double data rate mode at 400-MHz clock frequency.

With an eight-bank architecture and a 36-bit interface RLDRAM II can achieve a peak bandwidth of 25.6-Gbit/s excluding parity. The samples have a random cycle time of 20 nanoseconds.

Additional advantages of the RLDRAM II product feature set include; on-die termination, multiplexed or non-multiplexed addressing, on-chip delay locked loop, common and separate I/O, programmable output impedance and a 1.8-V core.

The specification of the RLDRAM, jointly developed by Infineon and Micron, was announced in May. RLDRAM II devices are available in a standard 144-ball FBGA.