Hsinchu-based eMemory Technology Inc. has already licensed its Neobit IP to Taiwan Semiconductor Manufacturing Co., Chartered Semiconductor Manufacturing, Renesas Technology and Powerchip Semiconductor Corp., one of its major investors. The firm is also in talks with several other chip makers and expects more licensing deals soon.

The companies are all keenly interested in what appears to be a novel cell structure that has the characteristics of EPROM -- used to store program data code -- but uses a simple, logic-based process that is more easily ported from fab to fab.

eMemory is targeting Neobit at MCUs, RF IDs and IC smart cards, and is also pushing it as a repair mechanism for bad pixels in CMOS imagers, for performance tuning in analog circuits or as a redundancy fuse circuit in commodity memory.

Although Neobit has the functionality of EPROM, the company is steering clear of any other comparisons to the widely used embedded memory, said eMemory President Charles Hsu.

"When you say EPROM, people will think it is a very complicated process and very costly," he said. "The technology is very difficult to port from generation to generation or from fab to fab, or from one technology to a derivative technology."

Neobit was designed to be technology agnostic, Hsu said. It can be implemented in analog, mixed-mode or high voltage processes. "You give me whatever your current technology is and we will just design this in," he said.

The company has worked on the technology for nearly two years, and was able to do a early tape out with Renesas last summer, during which the Japanese MCU giant saved nine masking layers on one product that used the Neobit structure, Hsu said. The company has also been working closely with Chartered Semiconductor.

If Neobit lives up to its claims, it could offer a simpler solution for 16- and 32-bit microcontrollers made on 0.25- and 0.18-micron processes. (It is currently being qualified on the 0.13-micron process at TSMC and Chartered.)

Its programming flexibility would allow for coding before or after processing, unlike ROM, which would give MCU makers greater latitude in controlling inventory. Hsu estimates Neobit process development would only lag logic process development by three to six months, much like ROM, but considerably faster than that for EPROM or Flash. "Our goal is to make this an industry standard. In 8-inch wafers and beyond 0.25-micron technology, we will make EPROM disappear," Hsu said.

Although the cell is one-time programmable, redundant blocks can be added to achieve a multiple programmable array. Even with redundant blocks, the area would generally be less than with EEPROM cells, Hsu said, because the size of a Neobit cell versus an EEPROM cell is 5-micron2 and 15 micron2, respectively, in a 0.35-micron process. Neobit's programming voltage at 0.35 micron is 6 to 6.5 volts versus about 10 volts for EEPROM, Hsu said.

The company is also quietly spinning a follow-on to Neobit called Neoflash. It will target low-density embedded flash applications, such as DVD baseband chips, where it is still too expensive to bring flash on-board for code storage.

The company is in the process of securing a patent on the Neoflash architecture so it is offering few details, but said more will be known in about six months.

In general, eMemory will add an erase circuit to the Neobit structure but still avoid making it a high-voltage device that would complicate the logic process. It will remain a single-poly, single-gate structure where the charge is stored in the oxide-nitride-oxide layer, unlike stacked-gate or split-gate structures.

Only three extra masks are needed to embed the Neoflash, instead of roughly nine, which will increase yield and bring down costs, the company claimed. "If our Neoflash is successful, it will be a revolutional technology because you can use the logic process to embed the flash," Hsu predicted.

By: DocMemory
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