Tuesday, November 25, 2003
Using 65-nm design rules, Intel Corp. announced Monday (Nov. 24) that it has made fully functional 4-Mbit SRAMs with a cell size of 0.57 microns2 — small enough to maintain Moore's Law of density doubling every two years.
Senior fellow Mark Bohr said Intel remains on a two-year schedule for developing the 65-nm process, with first commercial microprocessor products expected in 2005. Intel is in early production now with its 90-nm processors.
The cell size for the 90-nm test SRAMs came in at 1 micron2 two years ago, he said. Though Intel is not in the SRAM business, Bohr said SRAMs are "a great way to catch defects" in the process.
Asked if Moore's Law could remain in force for the next decade, Bohr said, "I personally find it very encouraging that generation after generation we come up with techniques, such as new mask making methods or strained silicon at the transistor, that help us remain on Moore's Law."
Intel's internal mask shop employed alternating phase shift masks (APSM) for the test SRAMs. The masks are much more expensive than more widely used attenuated phase shift masks. Bohr said mask costs, for high volumes Intel achieves with its microprocessors, remain "a relatively small part" of the overall cost of production.
Intel was able to make the test SRAMs with a newer generation of advanced 193-nm scanners at its Hillsboro, Ore., development fab, called D1D.
Bohr said Intel has not disclosed whether it uses alternating phase shift masks for its 90-nm designs, adding that the use of APSMs at the 65-nm node is Intel's initial announcement on the use of that technology.
Besides usimg more advanced masks, little appears to have changed radically between the 90-nm process and the 65-nm process. A similar form of low-k dielectric will be used, and the gate insulator remains a form of silicon dioxide. Intel reported earlier this month that it had identified a form of high-k oxide and metal gate electrodes that will be used at the 45-nm node in 2007.
Asked if Intel had introduced any new means of coping with transistor leakage currents, Bohr acknowledged that leakage becomes a larger problem as gate oxide is thinned. However, he offered no details about Intel's process refinements to control leakage.
Several analysts have speculated that Intel has been forced to redesign its Prescott MPU, which is in early procuction at 90-nm design rules, in order to deal with excessive power consumption.
By: DocMemory
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