Tuesday, December 16, 2003
Toshiba Corp. will begin offering by March engineering samples of a 65-nanometer embedded-DRAM technology jointly developed with Sony Corp. The two companies detailed the technology-which involves the smallest DRAM cell size ever reported, 0.11 square micron-at the International Electron Devices Meeting in Washington last week.
Their 32-Mbit memory device is fabricated on a 65-nm process called CMOS5 using six-layer copper wiring with low-k materials. "We are confident that our embedded-DRAM technology takes the lead by about two years among competitors," said Seiji Yamada, chief specialist in the Advanced CMOS Technology Group II at Toshiba's System LSI division.
Toshiba and Sony announced the key technologies-a transistor with a 30-nm gate, the embedded DRAM cell and SRAM cell, and multiple-layer wiring-for the 65-nm process last year. This year the team has come up with a practically operating device.
When DRAM cells shrink, it becomes essential to control the transistors' threshold voltage. To realize a high-performance DRAM cell, the threshold voltage should be maintained high and steady. That is realized by dense ion implantation at the transistor section, but at the same time, the dense ion implants cause leakage of electric charge at the memory capacitor, which deteriorates data retention.
The Toshiba and Sony team resolved this issue by means of a tilted implantation method that inserts a boron ion at a certain angle over the gates. Ions are implanted more densely on both sides of narrow gates; the opposite occurs with wide gates. This stabilizes the resulting threshold voltage, making it "almost flat," said Yoshinori Matsubara, a specialist in Toshiba's Advanced CMOS Technology Group II.
The method also serves to block ions from the memory capacitor section, the companies said. Thus, the team claimed that even the small, 0.11-square-micron cell has adequate threshold voltage and data retention.
Toshiba and Sony have been collaborating on 90-nm and 65-nm process technology development since April 2001. The second development phase, 65-nm process technology, is scheduled for completion in April.
Toshiba plans to begin sampling the 65-nm embedded DRAM in the first quarter, but Sony has not disclosed its fabrication plans. The company is now installing production equipment for 300-mm wafer lines at Nagasaki. Sony will use devices built on the CMOS5 process for its own products first, before selling on the merchant market.
By: DocMemory
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