Providing a parallel clocking scheme differs from parallel processing data in that the parallel clocking scheme is applied to the timing and minimizes each “timing drift” in the clock signal throughout the chip. This can lead to larger size system-on-chips.

In a paper delivered at the International Solid State Circuits Conference here on Wed. (Feb.18) NEC researchers detailed how this parallel clocking provides a seamless SoC whose IP cores are synchronized while having different operating frequencies. A chip might have one IP core that is suitable for sequential processing whose operating frequencies was 10 GHz and also have four IP cores that are suitable for parallel processing whose operating frequencies are 2.5 GHz and are fed from the same clock signals.

The researchers reported on a test chip fabricated in a 0.18-micron CMOS process that has clock lines distributed in five sections, each composed of a buffer and 3-mm interconnections. Compared to conventional clock distribution the buffers reduce clock skew by 85 percent when 2.5-Ghz four-phase parallel clocking is used. A multiphase flip-flop circuit is used for the parallel clocking, in a two pulsed-latch and two push-pull configuration.

“NEC believes that as the result of finer wires and ever higher performance future chips will need to implement this technological paradigm shift based on the parallel clock concepts,” said Masao Fukuma, vice president of NEC Corp.

“We are confident that we can track the ITRS [International Technology Roadmap for Semiconductors] for the required clock frequency all the way to the 22-nm processing node using this phase averaging technique, “ said Masayuki Mizuno, assistant manager of NEC's Silicon Systems Research Laboratories (Kanagawa, Japan).

By: DocMemory
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