Friday, February 20, 2004
Intel is using today's (Feb. 19) Intel Developer Forum as a stage to unveil details on its first flash memory device developed in its 90-nm process node.
Interest in moving memory and processor architectures to 90-nm technology has been a hot item in the communication sector, especially in the wireless handset market where designers are continually trying to fit more functionality in smaller and smaller system footprints. In a move to lead this trend, Intel has developed a single-bit-per-cell NOR flash memory device, code named Sibley, that provides a 2X size reduction over existing 130-nm parts, said Pete Van Deventer, director of marketing in Intel's Flash Memory group.
One of the reasons that Intel can provide such a large reduction in size at 90-nm lies in the amount of memory cells it can pack on a wafer. According to Van Deventer, the company can pack approximately 100 dies per wafer in a 130-nm process. In a 90-nm process, however, the company has shrunk die size in half, packing approximately 216 dies per wafer, he added.
Intel is also seeing a performance boost at 90-nm. While the company would not reveal specific performance numbers, Van Deventer said that Sibley will offer two times the read performance and four times the write performance over past NOR devices.
Intel will start sampling its Sibley device in the second quarter of 2004 and plans to move the part to volume production in the third quarter. At the same time, the company is also developing a two-bit-per-cell part in its 90-nm process. This part is expected to start sampling in the second-half of 2004, Van Deventer said.
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