Texas Instruments plans to sample its 65nm process technology in Q1 2005, the company said today, detailing the next-generation move.

The Dallas-based company expects 65nm to shrink 90nm designs by half and boost transistor performance 40 percent. Power leakage is also expected to be reduced from idle transistors by a factor of 1,000. The company has 4Mbit SRAM memory test arrays functional today, and plans to sample a wireless product built with the new process by April 2005, TI said.

"TI's 65nm CMOS process doubles the transistor density over our qualified 90nm production process and positions Texas Instruments for a leadership role in delivering the benefits of 65nm to customers early next year," said Hans Stork, TI's CTO, in a statement. "Along with the tremendous increase in functionality TI will offer at 65nm with highly integrated SOC designs, we are taking significant steps to lead the industry in managing the power those designs consume."

As part of its power-control strategy, TI plans to introduce its SmartReflex dynamic power management technology, which automatically scale power supply voltage, at the 65nm node in chips for wireless applications. Other power techniques TI will use at the 65nm level include back-biasing of SRAM memory blocks and retention flip-flop circuitry that allows the voltage to drop extremely low without requiring a rewrite of the logic for up to a total 1,000-fold reduction in leakage power.

The 65nm process includes up to 11 layers of copper interconnect integrated with a low-k dielectric, Organo-Silicate Glass (OSG), that has a k dielectric constant of 2.8, TI said. Other improvements combining to drive performance and minimize leakage in both the NMOS and PMOS transistors include process induced strain on the transistor channel during chip processing to increase electron and hole mobility, nickel silicide to lower both gate and source/drain resistance, and ultra-shallow source/drain junctions, according to the company.

TI is developing the 65nm process for both 200mm and 300mm production, with qualified production expected in late 2005. A technical paper on the 65nm low power process will be presented at the VLSI Symposium in Honolulu, Hawaii, in June.

By: DocMemory
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