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TSMC runs into problem with low-k


Wednesday, April 28, 2004 On the way to adopting low-k dielectrics, the world's largest foundry has run smack into a problem that is proving difficult to solve. Although Taiwan Semiconductor Manufacturing Co. Ltd. claims that it has resolved the issue of collapsed vias, there is no guarantee that it will go away as design rules scale to 90 nanometers and beyond, when low-k materials will be used more widely.

In the last few months, TSMC has battled reliability issues in the back end of the line. Because of differences in the way low-k materials expand during thermal stress, some clients' chips failed high-temperature tests.

TSMC, the first foundry with limited volume production of low-k in-tegrated circuits, has shipped approximately 10,000 eight-inch wafer equivalents, populated with 130-nm devices employing Applied Materials Inc.'s Black Diamond low-k material.

Low-k dielectrics deliver about a 10 percent performance improvement over fluorinated silicate glass, the more prevalent insulator, company officials estimate. TSMC spent much of 2002 and 2003 dealing with the expansion issues that arise in part when the die is packaged. At that point, the interconnect stack is put under mechanical and thermal stress, and the different coefficients of thermal expansion of the low-k material ¡ª compared with silicon, copper and packaging materials ¡ª created reliability issues, particularly in the vias.

Toward the middle of last year, TSMC (Hsinchu, Taiwan) thought it had solved most of those issues, and customers like Agere Systems Inc., which used TSMC's low-k process for a line of DSPs, trumpeted its success in being among the early adopters of low-k.

In a speech at last week's TSMC 2004 Technology Symposium here, Jack Sun, the foundry's vice president of logic development, declared, "We are the leader in using low-k."

But Manny Alvarez, a chip design manager at Newisys Inc. here, reopened the reliability issue at the Austin symposium. Newisys is developing a server line based on Opteron processors from Advanced Micro Devices Inc.

The ASIC designed by his team controls a multiprocessor server and "needs all the performance it can get," Alvarez said. Newisys targeted the design to the low-k 130-nm process at TSMC.

But earlier this year, the chip failed TSMC's reliability tests, where devices are cycled for up to 10,000 hours at temperatures as high as 150¡ãC. The problem was a familiar one: collapsed vias.

In Austin, T.Y. Chu, a marketing manager in TSMC's advanced technology division, insisted the failures Alvarez cited had been limited, affecting "only a few" of the 10 customers using Black Diamond.

Chu said TSMC discovered similar problems in "a few chips, fewer than four," all of which face high-temperature operating environments such as the Newisys server.

To solve the problem, TSMC went back to its library and memory compiler vendors, Artisan Components Inc. and Virage Logic Corp., to ask them to create redundant vias in the SRAM cells. Chu said TSMC has revised its Web site to create a separate set of design and IP recommendations for customers choosing the low-k dielectric, as opposed to those using the more prevalent fluorinated silicate glass (FSG) insulator.

Alvarez said the problem will not seriously impact Newisys. It expects to go through several revisions of its design before asking TSMC to begin commercial production. That will give the design team time to switch back to the low-k process after making some samples with FSG.

"We were pretty far down the line when this happened in early January. But it is really just a minor blip, and we expect to get back to low-k," Alvarez said.

Chu, a packaging veteran, said problems with mismatches in the coefficient of thermal expansion have "slowed down the whole semiconductor industry" as it moved to low-k dielectrics.

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