Atmel announced the availability of its first rad-hard in-system reprogrammable 3.3V FPGA, with built-in Single Event Upset (SEU) protection.

Upgraded from the AT40K40AL, a commercial SRAM-based FPGA, the AT40KEL040 has been re-designed to meet the stringent radiation requirements of space applications.

Developed for low gate count rad-hard designs, the AT40KEL040 offers up to 50K usable ASIC gates and 18-Kbit user-configurable SRAM blocks. It is an alternative to mask configured ASICs offering an easy development flow with no non-recurrent engineering (NRE) cost, shorter time-to-market and no minimum order quantity. The AT40KEL040 is the first product in a family of Atmel rad-hard FPGA, which will eventually enable system makers to develop customized designs up to 200K usable ASIC gates, for aerospace electronics, robots, scientific instruments, or embarked systems.

The device combines rad-hard capabilities, a latch-up threshold higher than 70-MeV.cm²/mg and a total dose in excess of 200 Krad, with a 60MHz system speed over the full military temperature range. Hardened by design, the AT40KEL040 configuration memory has a very low sensitivity to SEU, resulting in an upset rate lower than 3E-6 error per device per day in the worst orbit conditions. This innovative built-in SEU protection allows the user to design his/her application without using time-consuming mitigation techniques that can triple FPGA used gate count, thus saving expensive development resources and FPGA cost.

Specifically designed for compute-intensive DSP functions, the AT40KEL040 includes features such as user-configurable SRAM blocks. This single/dual port synchronous/asynchronous SRAM operates at 18ns. The architecture is optimized for efficient and ultra-fast array multipliers (up to 32MHz) implementation. The AT40KEL040 also offers the ability to implement cache logic design, where part of the FPGA can be reprogrammed without loss of register data, while the remainder of the FPGA continues to operate without disruption. This in-system dynamic reconfiguration ability is a direct result of the RECONF project, funded by the European Commission.

The chip is currently available in either 130 or 240 PCI-compliant I/Os, housed in MQFPF160 and MQFPF 256 packages, respectively. On request, the company can offer up to 384 I/O capability in larger packages.

By: DocMemory
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