Nios-II, the second generation of Altera Corp.'s soft processor core, will address the test and verification issues of its predecessor, according to the FPGA company.

Unveiled this week, Nios-II has several times the performance of Nios, but perhaps more importantly the user experience has been simplified. "Nios was highly configurable -- you could build not just peripherals but also the internal structure [of the processor]," said Paul Hollingworth, marketing director at Altera. "But it was a bit of a nightmare to test and verify."

The popularity of Nios has come as something of a shock to Altera. The company said it sold more than 12,000 development kits in the first three years, and is still selling over 1,000 kits per quarter. "Some customers are using Nios as the core datapath processor, including parallel processing with custom instructions," said Hollingworth.

The threat of hardware obsolescence is another driver for Nios, he said. "People are hugely concerned about obsolescence. One of the unexpected things we have found with Nios was people knew it wouldn't be made obsolete," he added. Once customers have the design kit and source code, the processor can be continually used, migrating from one FPGA architecture to another.

In an effort to simply Nios' implementation, Nios-II comes in three flavors: fast, standard and economy. At the fast end Altera promises 200MIPS from 1,800 logic elements. "Nios as originally envisaged was a housekeeping processor; now we're moving into ARM9 territory," claimed Hollingworth.

Meanwhile, the economy core uses just 550 logic elements to deliver around 20MIPS, a similar speed to the first Nios, but with half the size. Placing the economy Nios into a Cyclone FPGA would use up around three per cent of the available logic. The fast Nios in Altera's top end Stratix device consumes one per cent of the logic.

The three implementations of Nios-II are actually quite different in their structure. For example, the fast version has a six-stage pipeline, a single cycle multiplier and dynamic branch prediction. The standard has five stages, three-cycle multiplier and static branch prediction. The economy version has none of these advanced features, making do with a software multiplier.

When it comes to caches, again the economy misses out completely. The fast has configurable instruction and data caches; the standard has a configurable instruction cache. Despite these differences all three processors maintain code compatibility, but not with the original Nios; its code must be recompiled to run on the new devices.

Development tools have also been updated: "People demanded better software development," said Hollingworth. "We now have a full integrated development environment (IDE), debugger, real-time operating system and TCP/IP stack."

These all come for free with the Nios development kit, which remains priced at $995. There are currently two versions of the kit, one for Stratix FPGAs and one for Cyclone. The kit gives developers a perpetual license for Nios with no royalties.

The IDE sits alongside Altera's existing Quartus FPGA development software and SOPC Builder, its tool for configuring processor/bus-based systems.

"With Nios a lot of our customers were hardware engineers, plus a few software engineers," said Pat Mead, technical marketing manager. "As we go up in MIPS value, we have to do more for the software engineers."

SOPC Builder allows the processor, or many of them, to be configured on Altera's Avalon switch fabric bus, along with peripherals from a library, according to the company.

One of the key aspects of the IDE and SOPC Builder is the ability to add custom instructions, according to Altera. Once a software bottleneck is identified the errant code is removed and replaced with a custom instruction called as a C subroutine. SOPC Builder configures the new hardware block on the bus and imports the VHDL or similar code for that block into the Quartus tool.

By: DocMemory
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