Thursday, June 17, 2004
Renesas Technology said it has developed an SRAM memory cell that can reduce soft error rates at the same time as reducing cell size and power consumption.
The so-called 'SuperSRAM' technology would be put into commercial production for a 16M-bit low-power SRAM for mobile applications, with a 32-Mbit device to follow within this fiscal year, Renesas said.
The memory cell allows the fabrication of compact SRAMs which Renesas expects to displace psuedo-SRAMs, which have a DRAM core, in mobile applications. The compactness of pseudo SRAMs are attractive for cost considerations but the need to refresh the memory drives power consumption up. Similarly the static nature of SRAMs minimizes power consumption but SRAMs built in advanced process technologies have problems with retaining data due to soft errors.
The superSRAM replaces the two load MOS transistors of a conventional SRAM with two thin-film-transistors located above the other transistors, and it includes two cylindrical DRAM-style capacitors stacked on top of the node, Renesas said.
The design achieves a memory cell size of 0.98 square microns in 0.15-micron manufacturing process, Renesas claimed. The use of DRAM cylindrical capacitors at the storage nodes has enabled capacitance to be increased compared with normal CMOS type SRAM, and provides a structure in which soft errors do not occur.
In addition, a data retention current of less than one microamp has been achieved, Renesas said. Fabrication is possible using existing process technologies, which should enable a speedy introduction of devices into the market.
By: DocMemory
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