Monday, June 21, 2004
Samsung Electronics has developed a form of packaging for integrated circuits that is applied at the wafer level. It improves chip performance, Samsung claimed, while avoiding the expense of substrates, lead-frames and die and wire bonding materials and machines.
Samsung said that its wafer-level packaging (WLP) meets JEDEC chip-scale packaging ball-grid specifications and that it would apply the WLP to 512-Mbit DRAMs that conform to the DDR2 standard.
WLP, unlike conventional package technology, builds the package layer directly on the wafer by incorporating fabrication process. Two patterned inter-layer dielectrics and a metal layer replace the conventional package substrate. Ball grids give the appearance of a chip scale package (CSP).
WLP packaged DDR2 DRAMs can replace the same memories in CSP packaging without further modification, Samsung said.
By: DocMemory
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