Thursday, June 2, 2005
Japan's Hitachi Ltd. and Renesas Technology Corp. rolled out a new three-dimensional (3D) packaging technology that claims to use a through-hole interconnection method to enable chips to stack and bond at room temperature.
"The new technology eliminates the need for wire bonding and reduces package thickness by more than 60 percent for the most advanced system-in-packaging (SIP) products," according to the companies. "The method offers a new packaging technology option for developing 3D-stacked SIP products."
With this new packaging technique, chips that are between 30- to 50-micron thick are fashioned with through-hole electrodes between the top and bottom sides and gold stud bumps. It then allows the bumps and through-hole electrodes to connect by applying a compressive force at room temperature.
By: DocMemory
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