As part of a push to proliferate its “Power Architecture” microprocessors, IBM Corp. showed off its PowerPC 970MP, a dual-core version of an earlier design, this one aimed at applications that require 64-bit and symmetric multiprocessing (SMP) with ranges from 1.4 to 2.5 GHz.

The processor was unveiled at a power-focused event in Tokyo on Thursday.

Designed for entry level servers and embedded applications, IBM also said the processor contains power-saving features for dynamically controlling the system power thanks to its 64-bit power architecture as the foundation.

The increased computing density of the PowerPC 970MP is meant to improve performance for applications such as HPC clusters along with demanding embedded system applications like high performance storage, single board computer and high performance networking applications, the company explained.

Each of the two 64-bit PowerPC 970MP cores has its own 1MByte L2 cache, to allow for a range of performance and power operating points that can be selected dynamically to match system processing needs. The frequency and voltage of both cores can be scaled downward to reduce the power during periods of reduced workload.

For further power savings, each core can be independently placed in a power-saving state called “doze,” while the other core continues operation. Finally, one of the cores can be completely de-powered during periods of less stringent performance requirements, the company explained.

IBM also announced low-power extensions to its PowerPC 970FX processor, targeted for applications needing a low-cost 64-bit processor with a sub-20 Watt power envelope and SMP. These extensions have operating power of 13W at 1.4GHz and 16W at 1.6GHz.

Designed to run at frequencies up to 2.7GHz, the PowerPC 970FX contains a 512KByte L2 cache, native 64-bit and 32-bit application compatibility and uses a high bandwidth processor bus capable of up to 7.1GBytes/second to keep the processor core and the SIMD/Vector engine fed with data.

The processor core can dispatch five instructions per cycle, and issue one instruction per cycle to each of its ten execution units, including two fixed point, two floating point, two load store, two vector and two system units. The L1 instruction cache holds 64 KBytes, the L1 data cache holds 32 KBytes, and each processor has its own dedicated 1MByte L2 cache.

Further, during its forum, IBM said Denali Software, HCL Technologies and Xilinx joined its Power.org group, which is dedicated to promoting IBM’s Power Architecture technology as a “preferred open-standard hardware-development platform for electronic systems for consumer electronics, networking, storage, military and automotive customers,” the company concluded.

By: DocMemory
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