It's not uncommon for the latest generation cell phones to incorporate DRAM, SRAM, NOR and NAND chips in one package. "There's not phones being designed, in terms of advanced (3G) phones, that don't have MCPs in them," Ericson said.

He noted that from a test perspective, this involves testing for known-good-die, but also a lot more. The different types of memory involve different timing domains and operating speeds, for example. And there's no existing test fixture designed to access a module containing four different types of memory and four or more chips.

But Agilent says it can test these very types of MCPs with a single insertion, as well as do it in parallel.

The V5500, with what Agilent has dubbed its Programmable Interface Matrix circuitry, features a whopping 16,384 pins per test head. It is designed to fully utilize x320 test handlers in order to test up to 320 NAND devices in parallel, or up to 256 high-pin-count NOR and MCPs in parallel.

Ericson suggested that the tester could test up to 512 NAND flash devices in parallel, but that test handlers don't exist yet for that many devices.

When testing MCPs, the V5500 tests each die within the package serially; only a subset of the total I/O pins required to test the high-pin-count MCP is used to test each individual die as a result, according to Agilent. The tester's resources are subsequently coordinated via the Programmable Interface Matrix, minimizing the hit to overall test time, the company says.

Ericson said that the company currently has two customer beta sites lined up for the V5500, and that it plans to ship those beta testers later this month.

By: DocMemory
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