In the laboratory, the team achieved a 1.4 picoAmpare standby leakage current for NFET and 0.3 picoAmpare for PFET. The researchers claimed these are the lowest leakage current ever achieved.

The NEC researchers targeted ultra low-power technology to reduce power consumption of system-on-chip devices to 1/30 of conventional chips, enabling the design of a battery lasting 10 times longer than present systems. The new technology is the core of NEC's "Ultimate Low Power" initiative, and it is applicable at both the 65- and 45-nm nodes.

Standby power was negligible compared to the operating power of transistors at 180 and 130 nm. In scaled-down devices, lower supply voltage reduces active power consumption but standby power consumption often increases due to higher leakage current. At 65 nm, leakage power consumption is expected to exceed active power consumption for many devices.

Therefore leakage current suppression is essential for low standby power (LSTP) devices used in low-power applications such as mobile products. The International Technology Roadmap for Semiconductors (ITRS) predicts that higher dielectric constant (high-k) material would arrive in gate insulator used in LSTPs around 2006. The NEC group demonstrated the low leakage with high-k (HfSiON) insulator film, and intends to implement the newly developed technology in its 65-nm node LSTP devices scheduled to be available in 2006.

"It is quite challenging to maximize the performance while realizing low power in 65-nm or 45-nm nodes. Our development is one solution for this issue," said Yasushi Yamagata, senior manager at the Advanced Device Development Division of NEC Electronics.

Standby leakage is the result of three factors: subthreshold leakage between source and drain, gate leakage and gate induced drain leakage (GIDL). To suppress the standby leakage, all three factors need to be lowered. The NEC team combined a body-bias sensitive configuration and high-k (HfSiON) gate insulator film to solve the problem. The body-bias configuration is effective in reducing sub-threshold leakage, but does not reduce gate leakage and GIDL. Thus, its effectiveness is limited to relatively large standby leakage current of over the nanoAmpare-micron range.

At the leakage level required for LSTP devices, gate leakage and GIDL becomes larger than sub-threshold leakage. In low standby power mode, body-bias may increase GIDL, rendering the technique counterproductive.

"High-k gate insulator is known to lower gate leakage. And the use of high-k can also lower GIDL as well," said Yamagata.

The NEC team said it performed channel engineering to reduce GIDL and also demonstrated the effectiveness of the body-biasing scheme.

They said the combination of the body-biasing scheme and high-k film is applicable to devices used in high- performance servers, networks, PCs, consumer electronics and, especially, LSTP devices for mobile products, Yamagata said.

By: DocMemory
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