The core, with a number of options, is set to become available for licensing either from Mosaid (Ottawa, Canada) or from UMC, in the fourth quarter of 2005.

The design is intended to support both the DDR SDRAM standard with SSTL2 signaling and DDR2 SDRAM with SSTL18 signaling. It is also being designed so customers' products can interface to either DDR SDRAM or DDR2 SDRAM, without requiring two separately manufactured versions of the product. The memory controller IP will be delivered as a library of elements rather than a single, hardened block, Mosaid said.

The controller is intended to support chip-to-chip and chip-to- module configurations with speeds up to 800-Mbits per second per pin.

“UMC recognizes the important role that DDR memory plays in today's semiconductor industry applications. Mosaid is a valuable IP provider of DDR solutions, and we are pleased to work with this company to port its memory controller IP to our nanometer technologies. MOSAID's DDR2 SDRAM memory controller will be a welcome addition to our other 0.13-micron and 90-nanometer IP components available for implementation into customers' SoC designs,” said Ken Liou, director of the IP and Design Support division at UMC, in a statement issued by Mosaid.

“As the speed of standard DDR and DDR2 SDRAM memory devices increases, the benefits of Mosaid's and UMC's memory controller collaboration in reducing design effort and risk, and accelerating time-to-market become more compelling,” said Peter Gillingham, vice president and general manager of Mosaid's Intellectual Property Division, in the same statement

By: DocMemory
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