Renesas Technology Corp. said that it has developed a high-density capacitor-less twin-transistor RAM (TTRAM), which it claims achieves both high speeds and low power consumption.

It revealed the details last week at the 2005 IEEE Custom Integrated Circuits Conference (CICC) in San Jose. It is the second company, at least publicly, to announced that it is utilizing the floating body effect with silicon-on-insulator applications, a parasitic or unwanted effect that leads to current leakage in typical SOI applications, to do away with the capacitor in a memory cell.

In a 2Mbit test chip fabricated with a 0.13-micron silicon-on-insulator (SOI) CMOS process, the TTRAM achieved 250MHz operation in continuous data output mode and 133MHz in random access operation, while dissipating an active power of only 148mW. That's nearly 43 percent less than a conventional Renesas 0.13-micron CMOS process embedded DRAM, according to the company.

The fact that TTRAM memory cell operations don't require a step-up voltage or negative voltage, as DRAM cells do, makes the new cell design suitable for use with future finer processes and lower operating voltages, Renesas claimed. Furthermore, since it doesn't use a capacitor, TTRAM is compatible with future transistor process technology shrinks.

Furthermore, the TTRAM cell on the test chip was 0.33 microns square, more than 5 percent smaller than the conventional cell.

By: DocMemory
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