With its next generation Stratix II GX family, programmable logic company Altera has set out to unclog one of the biggest bottlenecks that face electronics systems today – transceivers.

The company’s new Stratix II GX FPGAs combine Altera’s FPGA fabric with up to 20 low-power transceivers operating between 622 megabits per second to 5.375 gigabits per second to meet the needs of new high-speed designs.

The devices’ transceiver blocks support PCI Express, serial digital interface (SDI), XAUI, SONET, Gigabit Ethernet, SerialLite II, Serial RapidIO and Common Electrical Interface 6 gigabits per second Long Reach and Short Reach.

With the launch of its new family, Altera is also offering intellectual property, system models, reference designs, signal integrity tools, and supporting collateral.

“Customers are already leveraging the best-in-class signal integrity of the previous Stratix GX family and the performance and density advantages of the Stratix II family,” said Danny Biran, VP of product and corporate marketing, in a statement. “In Stratix II GX FPGAs, we’ve extended the best features from these device families to meet the needs of the marketplace over the next several years.”

The third generation family offers multi-gigabit transceiver blocks, a big focus on signal integrity, low-power transceivers and flexible transceiver phase-locked loop and clocking modes. The devices also offer up to 132,540 equivalent logic elements and are built on TSMC’s 90 nanometer process technology.

Altera will sample the new family in Q1 2006, but customers can begin designs based on the family today using HSPICE models and Altera design software.

By: DocMemory
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