Thursday, November 3, 2005
Seventy-three percent of designers in China and Taiwan are designing ASICs at 180 nanometer or below, an increase of 21 percentage points from 2004, according to the results of an annual study by Global Sources Ltd. and Gartner Inc.
For standard IC projects, 52 percent of desingers in China and Taiwan are using 180 nanometer or finer line widths, 10 percentage points higher than 2004, according to the joint study, titled "Design Trends & Electronic Design Automation (EDA) Tools: Mainland China & Taiwan."
Global Sources and Gartner surveyed 378 engineers in China and 226 in Taiwan for a study that compares design trends and use of EDA tools in both regions.
According to the companies, the survey shows that 66 percent of Taiwan respondents and 69 percent of China respondents use four iterations or less in ASIC development, up 16 and 11 percentage points, respectively, from 2004.
"The use of fewer iterations shows that EDA tools are becoming more sophisticated and that engineers are becoming more skilled at using EDA software," said Nancy Wu, principal analyst of Gartner Dataquest's design and engineering group, in a statement.
The survey found that consumer products dominate design in China and Taiwan, with 35 percent of designers citing consumer electronics as their key focus, followed by communication projects (19 percent), industrial controls (16 percent) and computers/computer peripherals (15 percent).
By: DocMemory
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