The next implementation to be realized in the 90-nm node according to Infineon, currently in development, is for battery operated applications such as mobile phones and targeting exceptionally low power dissipation, stand-by power and leakage current performance. Infineon would not say whether this is an in-house development or a design for a specific customer.

Currently, the 90-nm process is operating at Infineon’s Dresden plant as well as UMC in Taiwan, ensuring supply chain flexibility.

“With its first 90-nm read channel product Infineon is well on track to deliver the next generation of ICs for the growing HDD market,” stated Peter Bauer, member of the management board and head of Infineon’s Automotive, Industrial and Multimarket business group.

Migration to 90-nm of the read channel core would allow the HDD industry to meet new requirements, including higher data rates, reduced power consumption and smaller die-size leading to advanced SOC solutions at competitive cost.

Infineon added the first tested read channel core silicon demonstrated that the PLL is able to reach up to 3.6GHz speed and that the analog front-end signal path allows for data rates up to 2.7Gbit/s, representing an increase of approximately 50 percent compared to read channels in 130-nm technologies.

The new read channel technology supports features such as perpendicular recording and leverages second generation reverse concatenation coding, which offers better signal-to-noise-ratio (SNR) performance for significantly improved storage densities.

By: DocMemory
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