Eight months after delivering first samples of a wireless device on its 65nm process technology, Texas Instruments (TI) Inc. said today it has qualified this process node and is moving to volume manufacturing.

The Dallas-based semiconductor manufacturer said its 65nm process delivers more processing performance for advanced applications in a smaller space without increasing power consumption. “TI’s model of driving our own in-house process technology development and initial production ramp in one TI fab and then fanning out to multiple fabs and foundries allows us to quickly achieve very high volumes for our customers,” said Dr. Hans Stork, CTO at TI in a statement.

“In this business, building some sample parts is good, but the competitive advantage goes to the supplier who can first deliver millions of high quality products,” he added.

TI first gave details about its 65nm CMOS process in early 2004, that aims to double transistor density over the its 90nm process, shrinking equivalent designs by half and boosting transistor performance by up to 40 percent.

In addition, TI’s 65nm process reduces leakage power from idle transistors while simultaneously integrating hundreds of millions of transistors that support both analog and digital functions in system-on-chip (SoC) configurations, the company said.

Since today’s advanced multimedia and high-end digital consumer electronics have increased processing demands, putting the focus on low power semiconductor technology development, TI said it has implemented its SmartReflex power and performance management technologies in its 65nm platform to allow a combination of intelligent and adaptive silicon, circuit design and software designed to solve power and performance management challenges at smaller process nodes.

By closely monitoring circuit speed, SmartReflex technologies can dynamically adjust voltages to meet exact performance requirements without sacrificing overall system performance, with the result being minimum power usage for each operating frequency, extended battery life and a reduction of heat produced by the device, the company noted.

Other techniques at 65nm reduce power consumed by transistors when they are idle, including times when mobile phones are in standby mode waiting to receive calls, including back-biasing of SRAM memory blocks and retention flip-flop circuitry that allows voltages to drop extremely low without requiring a rewrite of logic or memory content. Together, TI said these SmartReflex advancements can deliver up to a 1000 times reduction in power leakage.

To balance the needs of end products or applications, TI said it offers several process technology recipes such as the very low power offering that extends battery life in a range of portable products including 3G mobile devices, digital cameras and audio players with increasingly sophisticated multimedia features. A mid-range offering supports DSP-based products and TI’s high performance ASIC library geared toward communications infrastructure products. The highest performance version of TI’s 65nm process supports server-class microprocessors, the company added.

Finally, TI’s 65nm process allows up to 11 layers of copper interconnect integrated with a low k dielectric, OSG, with a k of 2.8 to 2.9. Other improvements include an induced strain on the transistor channel during chip processing to increase electron and hole mobility; nickel silicide to lower both gate and source / drain resistance, and ultra-shallow source / drain junctions, TI concluded.

By: DocMemory
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