Toshiba plans to boost its NAND flash output in 2006 and seek additional testing and packaging partners, according to a source that is familiar with the company. 

Toshiba announced that it would budget a capital expenditure (capex) of 225 billion yen for 2006, up 49% from its initially planned 151 billion yen. The chipmaker will boost its NAND flash monthly capacity by over 60% from 30,000 12-inch wafers to 48,750 by the end of 2006.

PTI is currently the sole memory testing and packaging house for Toshiba in Taiwan, and the company stated that despite aggressively ramping its capacity to meet the potential demand increase from Toshiba, it is still finding its capacity running short. PTI stated that it is considering to outsource some of its testing and packaging to keep pace with the strong Toshiba orders.

However, Toshiba is likely to outsource orders to other industry players in order to lower its testing and packaging costs, the source said. The potential candidates include King Yuan Electronics Company (KYEC) and Singapore-based United Test and Assembly Center (UTAC).

PTI admitted that Toshiba has sought additional packaging and testing houses and requested a price adjustment in late 2004 and the first half of 2005, as NAND flash priced dropped dramatically. PTI stated it did lower its prices.

By: DocMemory
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