The provision of a half-node step allows designers to improve performance and reduce the size of their designs by up to 19 percent. This can result in more die per wafer and more than 20 percent reduction in cost-per-die for certain designs, TSMC said.

The 80-nm process is a lithographic shrink of TSMC’s 90-nm process technology. As a consequence, this node supports most of the 90-nm libraries and intellectual property from TSMC and third-parties, requiring only simple re-characterization using 80-nm transistor models. Design rules are also a linear shrink from 90-nm.

The first flavor of 80-nm process in production is TSMC's high-performance GT process, which is due to be followed in February 2006 by the high-speed HS variant, followed by low power LP processes in March 2006. A special GC process, which provides both low active and standby power is due to become available in the third quarter of 2006, TSMC said.

TSMC first offered a half-node process at the 0.35-micron generation (with a shrink to 0.30-micron), followed by the 0.25-micron (half-node 0.22), 0.18-micron (half-node 0.16), and 0.13-micron (half-node 0.11) generations.

“Being first to 90-nm gave us the lead in performance and features and moving to 80-nm will improve our costs too,” said Rich Heye, general manager of desktop products at ATI Technologies Inc., in a statement issued by TSMC.

“Nvidia and TSMC have a longstanding strategic collaboration involving half-node technologies,” said Chris Malachowsky, senior vice president of engineering and operations at Nvidia Corp., in the same statement. “The ability to quickly port a design to a new technology with higher performance and a smaller footprint is a powerful tool in a competitive, consumer-oriented market.”

By: DocMemory
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