Geneva-based semiconductor manufacturer STMicroelectronics and South Korea-based DRAM producer Hynix today unveiled details of a speedier 4Gbit NAND flash memory that achieves a throughput of 36MB/sec., some 50 percent greater than previous results, produced by embedding the error correction processor within the memory die.

The device, which is to be featured at the International Solid State Circuits Conference today, incorporates a powerful embedded error-correction processor that can detect and correct up to five errors per page to ensure reliability and fast data throughput while simplifying the design of the memory system that improves on their 4Gbit product released last year.

High-density NAND flash memories are key components in the burgeoning market for portable mass-storage devices such as USB keys and MP3 players. This market is characterized by an ever-increasing demand for greater memory capacities and lower cost per bit.

“This innovative breakthrough will fast become standard in ST’s two bit per cell NAND flash roadmap,” said Carla Golla, general manager of ST’s NAND flash memory division, in a statement. “Moreover, we fully expect this type of approach to be implemented as an industry standard feature in 2-bit per cell devices, which are rapidly increasing their share of the NAND Flash market. This method realizes the cost advantages of multilevel cell technology, but without sacrificing system read throughput and reliability.”

Because data retention and memory cycling performance are reduced in multilevel cell (MLC) technology, MLC NAND flash memories normally require more complex error correction code (ECC) circuits executed as an algorithm by the system processor, said ST.

The technology employs a new approach in which a sophisticated ECC processor is embedded within the flash memory. The dedicated processor implements a well-known error correction technique called BCH (Bose-Chaudhuri-Hocquenghem) that is widely used in WLAN and other applications where multiple data transmission errors need to be reliably detected and corrected. As a result, the device achieves a read throughput rate of 36MB/sec., significantly greater than the best previously reported rate of 23MB/sec. before error correction.

The area occupied by the ECC circuitry is 1.3mm2, representing less than 1 percent of the total chip area and the average current drawn by the chip is less than 1mA, ST boasted. 

Both ST and Samsung are set to release 8Gbit NAND flash products later this year.

By: DocMemory
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