At the International Solid-State Circuits Conference (ISSCC) here, MIT claims that it has developed an ultra-low-power, 256-kilobit SRAM based on TI’s 65-nm process technology.

Using ultra-dynamic voltage scaling techniques — reportedly pioneered by MIT — the 0.4-volt, sub-threshold SRAM achieves 2.25 times lower leakage power, as compared to its six-transistor counterpart at 0.6 volts, according to TI and MIT. The SRAM also claims to incorporate 10 transistors per bitcell to enable operations down to 400-mV.

Ultra-dynamic voltage scaling is seen as a promising technology to reduce voltages at the sub-threshold level, said Dennis Buss, vice president of silicon technology development at TI (Dallas). The technology could enable ultra-low power devices at “the 45-nm node and beyond,” Buss said in an interview at ISSCC.

The collaboration between TI and MIT is partially funded by the Defense Advanced Research Projects Agency (DARPA). The development is part of an ongoing effort to create ultra-low power logic and memory devices for battery-operated products.

One of the factors in decreasing chip power consumption is improving the design of the transistor. Lost electricity leaking from these transistors, even when they are in their “off” state, is a problem that is a challenge for the entire industry.

Ultra-dynamic voltage scaling is also a way to enable devices with sharp on/off swings. MIT claims that it makes use of local voltage dithering (LVD) with sub-threshold operations to achieve ultra-dynamic voltage scaling.

Basically, it involves integrating embedded analog power switches on the chip. “The LVD technique uses embedded power switches to toggle between a small number of voltage levels at the local block level,” according to a paper presented by MIT at ISSCC in 2005. “Distributing these switches locally allows each block to minimize energy consumption using voltage dithering based on its own workload rather than a chip-wide workload.”

Merging the analog and digital world is easier said than done. TI and MIT, along with DARPA, are seeking to advance the technology by developing memory modules and other components.

One of the major challenges is to develop and integrate embedded DC-to-DC converters — or switching mode power supplies — on the chip, according to Buss.

In the ISSCC paper last year, MIT said that TI manufactured a CMOS, 90-nm adder test chip based on the technology. The 256-Kbit SRAM is build around TI’s new 65-nm process.

TI is also taking steps to reduce power and leakage. Last year, the chip maker claimed it had solved the problem of excessive leakage current at the 65-nm node with its so-called SmartReflex power and performance management technology.

It first introduced technology elements of SmartReflex at the 90-nm process node. The SmartReflex technologies are a combination of adaptive devices, circuit design and software designed to solve power and performance management challenges at smaller process nodes, TI said. This is instead of or in addition to specifically attacking gate leakage current through the use of high-k gate insulator materials, a quest that has been pursued by the industry for many years.

SmartReflex controls voltage, frequency and power dynamically based on device activity, modes of operation and process and temperature variation. This saves additional power without compromising end performance, TI said.

By: DocMemory
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