To address the increasing packaging complexities of cell phones, PDAs and other handheld products Singapore-based semiconductor test and advanced packaging service provider STATS ChipPAC Ltd. has added two die stack capability in its package-on-package (PoP) technology that allows integration of both analog and digital die in order to increase functionality and performance in a smaller overall footprint.

PoP is a three dimensional (3D) package technology in which two fully-tested packages are stacked during the board mount process to achieve higher functionality with a minimal increase in size, the company explained. The top package of a PoP is typically a memory component in a stacked die Fine Pitch Ball Grid Array (FBGA) configuration with package height of less than 1.2mm.

Until now, the bottom package of the PoP has been limited to a logic device in a single die FBGA package with less than 1mm profile height. Lands are arrayed on the top periphery of the bottom package to allow for the top package to be mounted onto it.

STATS ChipPAC said it has developed a two die stack version of the bottom package, referred to as VFBGA-POPb-SD2, which allows integration of two individual devices, such as a digital baseband processor and analog baseband, to add more functionality and reduce the overall space requirements and size of the underlying motherboard in handheld products.

In order to successfully integrate two die into a maximum 0.9mm profile height for the bottom package, STATS ChipPAC said it utilizes advanced wafer thinning, die attach, wire bonding and molding processes. Reduction in package size is achieved by using wire bonding technology which enables a smaller footprint for the stacked devices.

“With the increasing complexities of cell phones, PDAs and other handheld products, integrating both analog and digital die into the bottom PoP package provides increased functionality and performance in a smaller overall footprint,” noted Dr. Han Byung Joon, CTO of STATS ChipPAC in a statement.

“Our advanced wafer thinning, die attach and ultra low loop wire bonding techniques are optimized to enable the stacking of two die while meeting mold cap and package height requirements with tightly controlled warpage and ball coplanarity,” he added.

The VFBGA-POPb-SD2 meets accepted industry package and board-level reliability standards of a chip scale package, including stringent drop shock test requirements for handheld devices, and is compliant to lead-free and "Green" materials sets based on JEDEC Moisture Sensitivity Level (MSL) 2A standard at 260 degrees centigrade reflow temperatures.

By: DocMemory
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