Taiwan DRAM maker Nanya Technology plans to start sampling DDR3 DIMMs to its customers in the second half of this year, company spokesperson and vice president of global sales and marketing Pei-lin Pai said at SemiTech Taipei 2006.

Pai stated that Nanya does not expect DDR3 to contribute a significant portion of company revenues before 2008. This year, DDR3 DRAM chips will be manufactured utilizing 90nm technology, he said. Later on, when DDR3 enters the phase of mass adoption, the chips will move into a 70nm manufacturing process. This will presumably be in 2008, according to his current estimates.

Featuring a lower operating voltage (1.5V versus 1.8V for DDR2), an 8-bit pre-fetch architecture (DDR2 uses a 4-bit pre-fetch buffer) and on-die thermal sensors, DDR3 DRAM components are currently projected to provide data transfer rates from 800Mbps (DDR3-800) up to 1600Mbps (DDR3-1600). Other features will include CAS latencies ranged from 5 to 10 (DDR2 standard CAS latencies vary from 3 to 5) and power-saving modes known as PASR (Partial Array Self Refresh) and ASR (Auto Self Refresh), Nanya said. The DDR3 chips are expected to be available in two packages, 78-ball FBGA (for x4 and x8 components) and 96-ball FBGA (for x16 components).

DDR3 standard specifications are now under discussion within JEDEC, and final approval will probably be scheduled for the end of next year or the first half of 2008, Pai thinks.

This week at SemiTech Taipei, Nanya is showcasing a 240-pin 1GB DDR3 unbuffered DIMM designed to utilize 512-Mbit (128×4) DDR3-1066 chips and provide a maximum bandwidth of about 8.5GB/s (PC3-8500).

By: DocMemory
Copyright © 2023 CST, Inc. All Rights Reserved