The latest details on the schedule as well as work on a handful of new features and form factors—and a sneak peak ahead at the future—was the focus of the PCI-SIG annual meeting here this week (June 8-9).

Originally, the version 2.0 was set slated for release in late 2005. Now the group plans to conduct some in-depth tests based on the current 0.7 draft to arrive at a final version before the end of 2006.

Generally doubling speed in a given design means halving distance. Thus engineers have several open questions whether some connectors, board materials or other aspects of existing designs may have to change to accommodate the new speeds in the existing form factors.

"One of the big concerns is can version 2.0 handle all the Express form factors. There’s a whole new round of simulations going on to check that right now," said Michael Krause, an interconnect expert in Hewlett-Packard’s x86 server group. The simulations may take two months, he added.

What’s clear is "all the design budgets for 2.0 will be very tight," said Ramin Neshati, a technical program manager from Intel Corp. who has worked on version 2.0 from its inception.

The 400-psec jitter margin of the 2.5Gbit/s version 1.1 will shrink to 200 ps for version 2.0. Clocks and phase-locked loops will have to handle most of the narrowing restrictions, Neshati added.

One recent proposal suggests limiting Express 2.0 implementations to 85O-hms impedance on a pc-board. However, simulation tests may show the existing 100-ohms levels are adequate, at least in some implementations.

Meanwhile, designers have identified a handful of new features they will add to the 5-Gbit/s version. They include an access control feature to give software an ability to control packet routing on the interconnect and prevent hackers from spoofing and rerouting data, primarily for peer-to-peer traffic. The feature will be implemented for Express chip sets, switches and multifunction devices.

Another new feature will notify software in cases when a link automatically shifts to a lower speed or width. An update to the link-training state machine for Express will let software also control the configuration and adjust speed of Express 2.0 links.

Graphics chips need the new 5-Gbit/s speeds to drive higher performance as well as open the door to using the fast channels to eliminate graphics memory in favor of using the systems main memory—even when graphics are on a card off the motherboard. However, desktop and notebook computers may implement a mix of 5-Gbit Express for graphics and 2.5-Gbit Express for everything else for a few product generations.

In servers, both serial ATA and serial-attached SCSI standards are preparing a move up from 3- to 6-Gbit/s speeds that will want Express 2.0. In addition, multiport controllers for Ethernet, Infiniband and Fibre Channel will want the faster system link.

By: DocMemory
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