Tuesday, July 11, 2006
In the race to 65nm field-programmable gate array (FPGA) solutions, all eyes are on a single target: low power. Along with higher densities and better performance, semiconductor users have become accustomed to reduce power consumption as core voltage is reduced with every process technology node.
Developing new ways to manage power with each new generation of programmable logic technology has been a key component of Altera Corp.’s research and development efforts. Although the company’s archrival, Xilinx Inc., was first to launch its 65nm FPGA solution, Altera is confident that it will continue taking the lead in the market for products made on advanced processes.
In a press conference recently held in Hong Kong, the company traced its progress through eight test chip iterations over a three-year period, bringing them to Stratix III test devices, the next-generation FPGA solution that will deliver significantly higher density with as much as a 20 percent performance boost, and power savings that range from 30 to 70 percent compared to the older versions.
Robert Blake, VP of Product Planning at Altera, said, “Compared to 90nm, Stratix III features power consumption improvement of 50 percent at the same frequency.” He also made it clear that they aren’t shifting to 65nm technology just for the sake of it. “Timing is critical – it’s about delivering in volume when the customer needs it,” he said.
The first Stratix III trial chip was produced in April 2003, and the last verification chip was produced in May 2006. While the product is slated to be broadly available in 2007, there are fascinating architectural details already starting to emerge.
By: DocMemory
Copyright © 2023 CST, Inc. All Rights Reserved
|
