TSMC and Mentor Graphics have created a foundry-qualified process design kit (PDK) in support of Mentor's custom/mixed-signal IC design flow.

The companies noted that TSMC has long provided foundry-qualified design rule check (DRC), layout versus schematic (LVS), and parasitic extraction rule decks qualified for the Mentor’s Calibre platform, as well as Spice models for Mentor's Eldo Spice simulator.

Now, with this release of the 0.13-micron mixed-mode and RF Mentor-PDK for TSMC's CM013RG process, TSMC noted that it now supports the entire Mentor ICstudio custom/mixed-signal IC design flow.

This kit includes symbol library for Design Architect-IC schematic capture and parameterized layout generators for IC Station layout editor. This Mentor-PDK has been pre-qualified with the TSMC process. Design kits for the 90nm (nanometer) and 65nm nodes are currently being developed.

By: DocMemory
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