The technology calls for a nanoscale crossbar switch structure to be layered on top of conventional CMOS process. The technology is called by HP a ''field programmable nanowire interconnect'' (FPNI) — a variation on current FPGA technology.

The researchers presented a ''conservative'' chip model using 15-nanometer-wide crossbar wires combined with 45-nm half-pitch CMOS, which they said they believe could be technologically viable by 2010.

HP also used a model based on 4.5-nm-wide crossbar wires, which they said could be ready by 2020. The 4.5-nm crossbar architecture combined with 45-nm CMOS would yield a hybrid FPGA about 4 percent the size of a 45-nm CMOS-only FPGA. In this case, the clock speed will likely decrease, but so will energy per computation.

In the FPNI approach, all logic operations are performed in the CMOS, whereas most of the signal routing in the circuit is handled by a crossbar that sits above the transistor layer, according to HP.

Since conventional FPGAs use 80 to 90 percent of their CMOS for signal routing, the FPNI circuit is much more efficient; the density of transistors actually used for performing logic is much higher and the amount of electrical power required for signal routing is decreased, according to HP.

Because of the tiny sizes of the nanowires and switches in the crossbars, the researchers said they expected defect rates to be relatively high, according to HP. However, with the crossbar interconnect it is possible to route around defects, the researchers said.

Their simulations showed that an FPNI chip with 20 percent of the nanowires broken in random locations still had an effective production yield of 75 percent and did not present significant performance compromises, which should make it economically feasible to produce, according to HP.

By: DocMemory
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