SDRAM DIMM, RAMBUS RIMM Comparison

Perhaps, we should first look at the different working mechanism between an SDRAM DIMM and a Rambus RIMM module.

• Both systems are based on control clocking to precisely position the retrieved data.
• The SDRAM DIMM works on a 100Mhz clock (PC100) while the RIMM works on a 400Mhz clock.
• The SDRAM DIMM works on single data rate while the RIMM works on both edges of the clock to provide double data rate at two times of the clock frequency (800Mhz data).
• The SDRAM DIMM provides 64bits of data in parallel at each clock while the RIMM produces packets of 32bits data (at double clock edge) at each Rambus clock cycle. Therefore, it requires 2 Rambus clock cycles to get the same 64bits of data.
• SDRAM DIMM works on 64 data lines while the RIMM only work with a bus of 16 data lines.
• Rambus use a packetized bus reduction concept to minimize the bus width (number of signal wires) at the trade-off of increased data frequency.
• Therefore, the RIMM can be illustrated as a serial streaming technology instead of a parallel technology like the SDRAM DIMM.

Figure 1: It takes 2 Rambus clock cycles at 400Mhz to get the 64bits that an SDRAM will get in only one slow clock cycle 100Mhz.

The Basic SDRAM DIMM Tester Architecture

Figure 2 shows the typical SDRAM DIMM tester block diagram. It is a 64bit (72bit including ECC) tester built with 72bit algorithmic pattern generator, 72bit data comparitor, and 72bits of data driver/receiver. In additional, there is a set of address counter, control signal generator, refresh timer, and also a timing clock generator. Of that, the most complex unit is the algorithmic generator and the comparator.

Figure 2, Basic SDRAM DIMM tester

RIMM Tester built on the SDRAM Tester concept

In order to build a Rambus RIMM tester, a "RAC" (Rambus ASIC Cell) chip is required to translate the lower speed data (100Mhz) to the 800Mhz data rate. This custom chip acts as a "gear box" that translates the PC100 signals with a 4:1 gear ratio to four times the clock frequency and eight times the data rate. This ASIC also provides the voltage level translator to 1.8V. Since the Rambus channel works with both clock edges, twice the data from the PC100 signal generator is needed to keep up with the Rambus execution speed. That means 144 bits of data is required at the input side of the "RAC" chip. This translates into two PC100 SDRAM DIMM testers with time synchronization circuitry (hand shakes). Figure 3 shows the block diagram of the tester.

Figure 3, Rambus RIMM tester architecture

• The tester architecture requires 2 of the SDRAM DIMM testers with hand shake circuits. This design doubles the cost of the base signal generator.
• The "RAC" circuit is a license technology from Rambus, Inc, a one-time license fee plus per piece royalty payment is required.
• Additional cost of development for the custom "RAC" chip including tester features. This can vary between $300,000 to $500,000 up front.
• Complexity on PCB layout of the Rambus channel. Simulation analysis is required to minimize reflection. This leads to additional engineering cost.
• Cost of Rambus test socket. Presently, the only test socket available for testing RIMM starts at $3,500.

Conclusion