As memory device densities continue to increase, there are an increasing number of device combinations available to build high-density memory modules. Ultra-Slim Blade servers and embedded computing applications are just two market segments driving the need for high-density memory modules. An emerging trend for these applications is to use four-rank modules.

One of the major benefits of four-rank modules is that they can achieve the highest density using low density chip and lower cost components. These lower density components typically keep a pricing advantage over leading-edge high-density components for up to a year after their introduction.

Common methods to increase module densities include stacking, designing the module with multiple rows of devices per side, or a combination of both. These methods can be used for DIMMs, SO-DIMMs and other types of modules. As a result, system designers can double memory capacity without doubling the number of sockets. Alternately, they could keep the same memory capacity but reduce four or two-socket systems to two or one-socket systems and significantly reduce board space.

A comparison of a 4GB DDR DIMMs built with a variety of device densities is shown in the table below.

Another benefit of four-rank DIMMs is power savings. With the use of four ranks of x8 components, half the number of components is required for a 72-bit wide module

For a successful implementation of 4 Rank DIMM memory, System designers need to be aware of which processors and memory controllers are enabled to support four-rank modules.  Finally, it is necessary to note that byte five of the serial presence detect (SPD) describes the number of ranks on a module

Many system designers are now are rushing to find out what  “4 rank memory” is all about ?. We have the pleasure to introduce Bill Gervasi, the inventor/initiator of the “4 rank memory”, to furthur explain the details technical details regarding 4 Rank DIMMs.

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 4 Rank DRAM Modules

Addressing Increased Capacity Demand Using Commodity Memories

Bill Gervasi, VP DRAM Technology, SimpleTech

Chairman, JEDEC JC-45.3

January 19, 2006

DRAM Density Isn’t Keeping Up

The demand for more memory capacity in today’s computers, especially server class machines, is colliding with some frustratingly slow transitions in DRAM device density.  Mainstream servers want to pack up to 32GB per CPU, however the introduction of the 1Gb DRAM that would enable these servers has been delayed by a perfect storm of problems including the difficulty in yielding DRAMs from sub-100nm chip fabs.

4 rank modules, recently approved by JEDEC, address this gap by allowing up to 72 DRAMs per memory slot, enabling the 32GB per CPU capacity goal using commodity 512Mb DRAMs.  When the 1Gb DRAMs are finally in mass production, 4 rank modules double the reach again to 64GB per CPU.

No Magic to 4 Rank 

A rank of memory is the collection of DRAMs connected to a chip select signal from the memory controller,abbreviated CS.  Older controllers only provided two CS signals for every memory slot and a maximum of two memory slots, thereby limiting capacity per memory channel to 4 ranks.  A little simple math for a dual-channel controller and DRAMs each with a 4-bit wide data interface will explain why these controllers top out at 16GB.

Simply put, a 4 rank module has four CS signals per slot.  Newer memory controllers, anticipating the release of these modules, provided 8 CS signals per channel.  Motherboards for these controllers need only have routed the two extra CS signals per slot to enable 4 rank functionality.

A system detects the presence of a 4 rank module in a slot by reading the required serial presence detect (SPDEEPROM included on every JEDEC module and looks for the value in byte 5 of the SPD which contains the number of ranks on the module.  If the value is 4, it enables the extra two CS signals per slot.

How Fast Can 4 Ranks Run?

The address bus interface to 4 rank modules is straight forward even though twice as many registers are on a 4 rank module than a 2 rank or 1 rank module.  Designers should still simulate to confirm timing budget closure, but the data bus is often the more challenging problem.

Some careful design techniques on 4 rank modules make the 4 data loads on that module appear as a lumped load to the signals traveling on the motherboard.  Coupling this with careful use of the DDR2 DRAM on-die termination (ODT) capability, and asserting two ODT signals to each slot simultaneously, has enabled 4 rank per slot, 2 slot systems to achieve DDR2-667 levels of performance, also known as PC2-5300 at the module level for the 5300 MB/s peak throughput of this configuration.

This association of CS signals, the ODT signals, and the clock enabling CKE signals that are used to manage power must be understood by the motherboard designer and the controller programmer.  All JEDEC 4 rank modules explicitly define the exact assignment of signals to ranks of memory.  Since there are options in how controller signals are connected to module signals, designers must make themselves aware of this and program the controllers appropriately

DDR1 4 rank modules do not have on-die termination.  For DDR1 4 rank modules, the association between CS signals and CKE signals is the same as the DDR2 interface, without ODT considerations.

Carpe DRAM! 

The industry hunger for more memory shows no signs of slowing down while the time between DRAM generationsgrows longer with each chip density.  4 rank memory modules are the result of innovations spurred by this disparity but also the result of cooperation between numerous companies who contributed to the development of the standard specification.

DDR1 and DDR2 variations of the 4 rank standard are already proliferating through the industry, and the standards body is already well along with the definition of the 4 rank module specification for DDR3 systems as well.

 Article contributed by Bill Gervasi of Simple Technology Inc