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DRAM Physics 101

Tuesday, January 18, 2000 INTRODUCTION

As semiconductor geometry and line width gets smaller, we can theoretically build higher density DRAM memories within the same size of die. However, the challenge for the DRAM designer is not the transistor size, it is the push against limit of physics. It is the cost of adding complexity versus benefit of further miniaturization of the final product.


A DRAM cell consists of basically two transistor switches and a capacitor. When the first transistor is turned on, the capacitor gets its charge and retains a logical state of “1”. When the first transistor is turned-off and the second transistor is turned on to discharge the capacitor, the memory cell attends a “0” state. Since a small capacitor can only retain its charge for a short period of time, constant recharging (or refreshing) of the capacitor is needed. That is why it is called “Dynamic Random Access Memory”.


A capacitor consists of two conductive plates separated by an insulator. When direct current is applied to the plates, they become electrodes holding positive and negative charges. The positive plate is called the anode and the negative plate is called the cathode. The electrical charge it can retain (capacitance) is determined by the surface area of the Electro and the property of the insulator (dielectric). The larger surface area of the electrodes results in larger capacitance which is measured in the unit of micro farad. The thinner the insulator will increase the capacitance since the electrons can get closer attached to each other. Likewise, the property of the material makes up the insulator also plays a large factor in the capacitance per fixed area.

Another factor on the quality of the capacitor is the withstanding voltage. That means the quantity of insulation to guarantee that the electrons will not jump through. Normally, the thicker the insulation, the higher voltage it will withstand. However, that capacitor will be physically bigger in size.


As the geometry of the DRAM shrinks, the area allowed for the capacitor is reduced. However, the capacitance on a DRAM cell must be maintained. That means the capacitors on the silicon chips must be redesigned for each generation of memory density and line width. As the available area reduces, a better capacitor must be designed. Basically, there are only two known ways of generating the same capacitance with less available linear area.

The first approach is to stack several capacitor layers together to get higher capacitance. Today, the most common practice is a 4 stack. Manufacturer found that the more stacks of the capacitor will require more process layers and thus higher cost. At the same time, the interconnection of the layers becomes problem as more metal layers are included.

The second approach is to cut a groove in the DRAM die and bury the electrode and insulator into that trench. Due to the vertical wall, the applicable area of the capacitor is greatly increased while the linear area remains the same. This is called the “Trench” technology. At the same time, the surface of the Electro is roughened up to gain more surface area.


Back at the 1 micron or higher geometry, silicon oxide is the key insulator. It has a dielectric constant of 4-8. When geometry goes smaller, there are needs for a better dielectric. aluminum oxide is used. Going into the sub-quarter micron, tantalum pentoxide (the material used in discrete tantalum capacitors) is used. They have dielectric constant of 8 and 26 respectively. Beyond the 0.12 micron geometry, DRAM manufacturers are experimenting with barium strontium titanate as well as the latest material used in Ramtron’s Ferro RAM process. These dielectric is reported to have dielectric constant up in 600-800 region. Process cost will definitely become higher.

Then there is also the issue of voltage breakdown of the dielectric. That is one of the reasons that the DRAM manufacturers are opting for lower and lower operating voltages.

Stability is another factor that can make the DRAM useless in the operation environment. Noise factor caused by these exotic dielectrics are difficult to overcome. Several companies are touting with the technology to build the switching transistor closer to the capacitor. IBM and Infineon are building the transistor on the wall of the trench just to reduce the noise.


Back in the 1980’s, Texas Instruments had made a 4Mbit trench DRAM based on 0.7 micron geometry. Due to noise and stability, it never made inroad to the market. IBM and Infineon had recently formed a partnership to re-develop a new trench process promised to fixed the problems. Toshiba, who was formerly a member of the joint-venture in trench, had pulled out last year declaring that they might never see the day-light on trench technology.

On the other hands, Samsung semiconductor had announced new technology based on an extension of the stacking technology. Other Japanese manufactures like Mitsubishi and Fujitsu are also putting their research money on extending the stack capacitor.


Higher dielectric and more complex structures are expected for the future generation of DRAM. It is expected that the R & D cost for the 1 Gigabit DRAM will exceed $10 billion. At this price tag, joint-venture and consolidations in the industry will be the only possible way. When coupled with the high cost of lithograph equipment, the cost per bit of DRAM memory will soon hit a plateau. We might have to ask the question “Are we at the limit of the laws of physics?”

By: Cecil Ho
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